Illustrated in FIG. 1 is a conventional integrated synthesizer and voltage controlled oscillator (VCO) 100 comprising three input terminals: a clock (CLK) input terminal 102a, a serial data (DATA) input terminal 102b, and a load enable (LE) input terminal 102c. An example of an integrated synthesizer and VCO 100 is the ADF4360-0 manufactured by Analog Devices, Inc.
Integrated synthesizer and VCO 100 receives serial data at DATA input terminal 102b and programs one of an R counter latch, an N counter latch, and a control latch. For each rising edge of a clock pulse received at CLK input terminal 102a, synthesizer and VCO 100 shifts a bit received at DATA input terminal 102b into a 24-bit shift register 110. When a signal at LE input terminal 102C transitions from low to high, synthesizer and VCO 100 transfers the data residing in register 110 to a 14-bit R counter 120, an 18-bit N counter 130, or a 24-bit function/control latch 140, depending upon the values of control bits present in the input data stream. Shifting the data to R counter 120 generally corresponds to programming of the R counter latch; shifting the data to N counter 130 generally corresponds to programming of the N counter latch; and shifting the data to function latch 140 generally corresponds to programming of the control latch.
FIG. 2 illustrates a timing diagram 200 of signals present at input terminals 102 of VCO 100. As illustrated, synthesizer and VCO 100 is configured to receive a 24-bit serial data stream 220 at DATA input terminal 102b. Synthesizer and VCO 100 receives the data serially from most significant bit (DB23) first to least significant bit (DB0) last. The two least significant bits (DB0 and DB1) are the control bits (respectively, having values C1 and C2) that determine which of the R counter latch, the N counter latch, or the control latch are programmed by the other bits (DB23 through DB2) of serial data 220. By programming the R and N counter latches, bits DB23 through DB2 are used to control a current (CP) outputted at CP output terminal 106a. FIG. 2 also illustrates timing characteristics of clock signal 210 (received at CLK input terminal 102a) and LE signal 230 (received at LE input terminal 102c).
Referring now to FIG. 3, there are illustrated three formats supported by integrated synthesizer and VCO 100 for the 24-bit data stream received at DATA input terminal 102b. Each of the three formats corresponds to a different function performed by integrated synthesizer and VCO 100. FIG. 3A illustrates the format of the 24-bit data stream 220 for programming the R counter latch; FIG. 3B illustrates the format of the 24-bit data stream 220 for programming the N counter latch; and FIG. 3C illustrates the format of the 24-bit data stream 220 for programming the control latch.
A 24-bit data stream in which control bits (C2,C1)=(0,1) must abide by the format, illustrated in FIG. 3A, for programming the R counter latch. In such a format, data bits DB15 through DB2, having respective values R14 through R1, are used to program 14-bit R counter 120. The 24-bit data stream is clocked into 24-bit data register 110 by clock 210, and, when LE signal 230 goes high, data bits R14 through R1 are sent from 24-bit data register 110 to 14-bit R counter 120. Data bits R14 through R1 specify a division ratio by which the frequency of an REFIN signal present at REFIN input terminal 104a is reduced by 14-bit R counter 120.
A 24-bit data stream in which control bits (C2,C1)=(1,0) must abide by the format, illustrated in FIG. 3B, for programming the N counter latch. In such a format, data bits DB20 through DB8 and DB6 through DB2, having respective values B13 through B1 and A5 through A1, are used to program N counter 130. More specifically, data bits B13 through B1 are used to program 13-bit B counter 139a of N counter 130, and data bits A5 through A1 are used to program 5-bit A counter 139b of N counter 130. The 24-bit data stream is clocked into 24-bit data register 110 by clock 210, and, when LE signal 230 goes high, data bits B13 through B1 are sent to 13-bit B counter 139a and data bits A5 through A1 are sent to 5-bit A counter 139b. Data bits B13 through B1 specify a value “B” used by B counter 139a to reduce the frequency of a vn signal input to N counter 130. Data bits A5 through A1 specify a value “A” used by A counter 139b to also reduce the frequency of vn.
A 24-bit data stream in which control bits (C2,C1)=(0,0) must abide by the format, illustrated in FIG. 3C, for programming the control latch. In such a format, data bits DB23 and DB22, having respective values P2 and P1, are used to program prescaler 132. The 24-bit data stream is clocked into 24-bit data register 110 by clock 210, and, when LE signal 230 goes high, data bits P2 and P1 are sent to prescaler 132. Data bits P2 and P1 program prescaler 132 by setting a value “P” used by prescaler 132 to reduce the frequency of vn.
As described above, various subcomponents of N counter 130 are used to divide a frequency of a voltage signal vn. Voltage signal vn is proportional to the difference between complementary voltage signals vOUT1 and vOUT2 output by VCO core 150. The N counter 130 divides down the frequency of vn by N=(PB+A). The reduced-frequency signal is applied to output stage 160. As also described above, R counter 120 is used to divide down the frequency of REFIN.
The phase of the output signal of R counter 120 is compared to the phase of the output signal of N counter 130 by a phase comparator 160a in output stage 160. The output of phase comparator 160a drives a charge pump 160b which provides, at CP output terminal 106a, current CP which may be applied to an external filter (not illustrated) to set VTUNE at input terminal 106b. 
The VTUNE drives VCO core 150 to produce complementary output signals vOUT1 and vOUT2, wherein fOUT1=[(P×B)+A]×fREFIN and fOUT1 is spaced in frequency by R (specified by data bits R14 through R1 stored in 14-bit R counter 120). The frequency, fOUT1, is the output frequency of VCO core 150; P is the present modulus (e.g., 8/9, 16/17, etc.) of dual-modulus prescaler 132 specified by data bits P2 and P1; B is the preset divide ratio (3 to 8191) of binary 13-bit counter 139a specified by data bits B13 through B1; A is the preset divide ratio (0 to 31) of binary 5-bit swallow counter 139a specified by data bits A5 through A1; and fREFIN is the external reference oscillator frequency of REFIN input at input terminal 104a. 
Because control bits (C2,C1) are present at the end of the input serial data stream provided to DATA input terminal 102b, integrated synthesizer and VCO 100 waits to receive the entire 24-bit serial stream before operating on the data present in bits DB23 through DB2. In other words, integrated synthesizer and VCO 100 does not know which of the three latches to program with the 24-bit serial stream entering at DATA input terminal 102b before the final two bits (control bits C2 and C1) are received. Thus, a new computation of fOUT1 must wait until all of the bits of 24-bit serial stream have been received. The performance of the integrated synthesizer and VCO 100 is, therefore, reduced.